Multiple Errors Detection Technique for RAM

This paper introduces a new technique for multiple errors detection for RAM based on the Self-Adjusting Output Data Compression (SAODC). The proposed technique needs an extra block to be injected into SAODC unit. This block performs evaluation of supplementary bits, which are added to each compressed address. All pairs of address bits iterated and their product gives the supplemented bit. Unlike an earlier works, our technique allows to detect multiple errors of even error rate. Besides, we consider comparative implementation and hardware overhead for proposed and standard approaches.