DocumentCode
3314474
Title
Using Fourier analyses to enhance IC testability
Author
Thibeault, C.
Author_Institution
Dept. of Electr. Eng., Ecole de Technol. Superieure, Montreal, Que., Canada
fYear
1994
fDate
17-19 Oct 1994
Firstpage
280
Lastpage
288
Abstract
In this paper, we explore the potential of FFTs in digital IC tests. The effects of three parasite contact types are investigated. Results show that unappropriate logical values on output voltages are easily detected and that FFTs on supply current can make detectable undesired contacts causing additional delays. Application of the method to technologies with non small quiescent currents and to large ICs is also discussed
Keywords
digital integrated circuits; FFTs; Fourier analyses; IC testability enhancement; digital IC tests; large ICs; parasite contact types; Circuit faults; Circuit testing; Current supplies; Digital integrated circuits; Fault detection; Flexible printed circuits; Frequency estimation; Integrated circuit testing; Logic testing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on
Conference_Location
Montreal, Que.
ISSN
1550-5774
Print_ISBN
0-8186-6307-3
Type
conf
DOI
10.1109/DFTVS.1994.630041
Filename
630041
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