A passive CMOS low-pass filter for high speed and high SNDR applications

Author

Payandehnia, Pedram ; Yeknami, Ali Fazli ; Xin Meng ; Chao Yang ; Temes, Gabor C.

Author_Institution

Electr. Eng. & Comput. Sci. Dept., Oregon State Univ., Corvallis, OR, USA

fYear

2015

fDate

24-27 May 2015

Firstpage

285

Lastpage

288

Abstract

A new passive switched-capacitor low-pass filter topology is presented. The sampling rate is high due to the reduced number of clock phases and switches connected to each capacitor. Also, this scheme decreases the filter nonlinearity. Verified by simulations, the noise analysis of the filter shows superior performance compared to active SC filters. These features, and a wide frequency tuning range, make the filter suitable for high-speed, low noise, and low power applications. A 7^th-order 400 MS/s filter was designed in 0.18 μm AKM CMOS technology. Simulations verify that it can achieve over 100 dB attenuation at 200 MHz frequency, while consuming only dynamic power.

Keywords

CMOS integrated circuits; attenuation; integrated circuit noise; low-pass filters; nonlinear filters; passive filters; switched capacitor filters; AKM CMOS technology; active SC filters; clock phases; filter nonlinearity; frequency 200 MHz; frequency tuning range; noise analysis; passive CMOS low-pass filter; passive switched-capacitor low-pass filter topology; size 0.18 mum;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2015 IEEE International Symposium on

Conference_Location

Lisbon

Type

conf

DOI

10.1109/ISCAS.2015.7168626

Filename

7168626