Flip-Flops and Scan-Path Elements for Nanoelectronics

Fault tolerant design has recently gained new attention due to the increasing volatility of nano-electronic circuits from transient fault effects. Latches and flip-flops are the potential sources of errors. Novel designs of fault-tolerant flip-flops encompass multiple latches, which can also be used to accommodate the double-latched scan for dynamic test. The resulting scan-path elements are fault-tolerant for functional operation and static scan test.