A low power 120-to-520Mb/s clock and data recovery circuit for PWM signaling scheme

Author

Eunho Yang ; Kyongsu Lee ; Jin-Ku Kang

Author_Institution

Dept. of Electron. Eng., Inha Univ., Incheon, South Korea

fYear

2015

fDate

24-27 May 2015

Firstpage

345

Lastpage

348

Abstract

This paper presents a 120-to-520Mb/s clock and data recovery (CDR) circuit that utilizes pulse width modulation (PWM) signaling scheme. Compared to the conventional approach, the proposed retiming scheme improves sampling margin over 200%, which results in lower BER. The proposed idea has been simulated in a 65nm CMOS technology. The post layout simulation result has shown that recovered clock and data have 3.42ps and 7.55ps rms jitter at 500Mb/s data rate. The CDR circuit consumes 1.97mW (1.2V supply) at 500Mb/s of MIPI M-PHY signaling format.

Keywords

CMOS integrated circuits; clock and data recovery circuits; error statistics; integrated circuit layout; low-power electronics; pulse width modulation; timing jitter; BER; CMOS technology; MIPI M-PHY signaling format; PWM signaling scheme; bit error rate; bit rate 120 Mbit/s to 520 Mbit/s; clock and data recovery circuit; jitter; low power circuit; post layout simulation; power 1.97 mW; pulse width modulation signaling scheme; size 65 nm; time 3.42 ps; time 7.55 ps; voltage 1.2 V; Clocks; Flip-flops; Jitter; Logic gates; Phase locked loops; Pulse width modulation; Voltage-controlled oscillators; MIPI M-PHY; Pulse width modulation (PWM); clock and data recovery (CDR); low voltage differential signal (LVDS);

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2015 IEEE International Symposium on

Conference_Location

Lisbon

Type

conf

DOI

10.1109/ISCAS.2015.7168641

Filename

7168641