Image synthesis acceleration using field programmable gate arrays

The large capacity of field programmable gate arrays (FPGAs) with dynamic reconfigurabilities opens new possibilities in acceleration of the image synthesis. A special computing system, based on FPGA and design to implement the algorithms typically used in image synthesis, has been built at the Faculty of Computer Science and Information Systems, Technical University of Szczecin (Poland). For instance, the 3DDDA algorithm has previously been used for ray tracing and implemented in a dynamic FPGA processor, called PSWO. PSWO processor provides an experimental basis for implementing procedures and algorithms applied in the image synthesis. The results of tests and simulations conducted on a large Power Challenge Computer of SGL were further verified through implementation in an actual PSWO processor. An increase of the speed from several dozen to hundred times was achieved in the test cases