Title :
Which junction for advanced CMOS?-theory, benchmark and predictions
Author :
Skotnicki, Thomas
Author_Institution :
STMicroelectron., Crolles, France
Abstract :
In this paper, the theoretical considerations about junction design for advanced CMOS, to benchmark the most recent and advanced results, and make some predictions on the future needs are presented. Junction scaling is the key difference that grants better electrostatic integrity (essentially smaller DIBL) to SON/SOI and DG structures if compared with bulk. With the use of these structures, DIBL can be kept under control (<100 mV) down to 5-10 nm gate length.
Keywords :
CMOS integrated circuits; CMOS; benchmark; electrostatic integrity; junction design; junction scaling; Annealing; CMOS technology; Doping; Electrical capacitance tomography; Epitaxial growth; Laser theory; Physics; Plasmas; Solid lasers; Solid state circuits;
Conference_Titel :
Junction Technology, 2005. Extended Abstracts of the Fifth International Workshop on
Print_ISBN :
4-9902158-6-9
DOI :
10.1109/IWJT.2005.203865
