NMOS-junction integration study with ultra-high temperature non-diffusive laser annealing for the 45 nm node and below

Author

Pouydebasque, A. ; Dumont, B. ; Wacquant, F. ; Halimaoui, A. ; Laviron, C. ; Lenoble, D. ; El-Farhane, R. ; Duriez, B. ; Arnaud, F. ; Carron, V. ; Rossato, C. ; Pokrant, S. ; Salvetti, F. ; Dray, A. ; Boeuf, F. ; Skotnicki, T.

Author_Institution

Philips Semicond., Crolles, France

fYear

2005

fDate

7-8 June 2005

Firstpage

15

Lastpage

18

Abstract

This paper demonstrates that, for NMOS, the use of LSA and smart junction engineering enable to improve dramatically short channel effects (-65% in DIBL at L_g=45 nm due to lower X_j and DL) and I_on/I_off performance (+7% I_on at I_off=100 nA/μm due to steeper sub-threshold slope and reduced poly-depletion) compared to spike annealed N-MOSFETs. These results show the potential advantage of ultra-high temperature and non diffusive annealing such as LSA that may be necessary for the 45 nm technology and below.

Keywords

MOSFET; high-temperature effects; laser beam annealing; NMOS-junction integration; nondiffusive laser annealing; short channel effects; smart junction engineering; spike annealed N-MOSFETs; ultra-high temperature; Analytical models; Annealing; Ion implantation; MOSFETs; Optical device fabrication; Semiconductor lasers; Semiconductor process modeling; Solids; Temperature; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Junction Technology, 2005. Extended Abstracts of the Fifth International Workshop on

Print_ISBN

4-9902158-6-9

Type

conf

DOI

10.1109/IWJT.2005.203867

Filename

1598653