Drain structure optimization for highly reliable deep submicron nMOSFETs with 3.3 V high performance operation

Author

Matsuoka, F. ; Kasai, K. ; Oyamatsu, H. ; Kinugawa, M. ; Maeguchi, K.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

833

Lastpage

836

Abstract

A guideline for optimization of the n/sup -/ fully gate overlapped structure (FOLD) has been established. Its reliability and performance were investigated in comparison with optimized LDD (lightly doped drain) structure (op.LDD). It is found that the superiority in reliability for the two structures is reversed below 3.5 V, and the optimized FOLD structure (op.FOLD) has higher reliability than the op.LDD structure. This is due to a discrepancy between peak electric field and current flow caused by high controllability of the gate electrode of the FOLD structure at the n/sup -/ extension region. The op.FOLD structure achieves high performance on the trend at 3.3 V, in spite of nonscaled gate oxide thickness (11 nm), which results from TDDB limitation for 3.3 V operation.<>

Keywords

insulated gate field effect transistors; reliability; semiconductor device testing; 3.3 V; FOLD structure; TDDB limitation; current flow; deep submicron nMOSFETs; drain structure optimization; gate electrode controllability; high performance operation; n/sup -/ fully gate overlapped structure; peak electric field; reliability; Controllability; Electrodes; Guidelines;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237033

Filename

237033