Optimum low-voltage silicon power switches fabricated using scaled trench MOS technologies

Author

Shenai, K. ; Hennessy, W. ; Ghezzo, M. ; Korman, C. ; Chang, H. ; Temple, V. ; Adler, M.

Author_Institution

General Electr. R&D, Schenectady, NY, USA

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

793

Lastpage

797

Abstract

Optimum low-voltage silicon power MOSFET technologies with forward conductivities approaching the silicon limit are presented. Vertical scaled trench power MOSFETs with measured performances of V/sub DB/=55 V (R/sub sp/=0.2 m Omega -cm/sup 2/, k/sub DEV/=5.7 Omega pF) and V/sub DB/=35 V (R/sub sp/=0.15 m Omega -cm/sup 2/, k/sub DEV/=4.3 Omega -pF) were developed, where V/sub DB/ is the drain-source avalanche breakdown voltage, R/sub sp/ is the specific on-state resistance, and K/sub DEV/ is the input device technology factor. Measured performances are in excellent agreement with detailed two-dimensional device simulations.<>

Keywords

MOS integrated circuits; insulated gate field effect transistors; power integrated circuits; power transistors; semiconductor switches; 35 V; 55 V; LV power switches; drain-source avalanche breakdown voltage; forward conductivities; input device technology factor; power MOSFET technologies; scaled trench MOS technologies; specific on-state resistance; two-dimensional device simulations; Avalanche breakdown; Breakdown voltage; Conductivity; Electrical resistance measurement; MOSFET circuits; Performance evaluation; Power MOSFET; Power measurement; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237042

Filename

237042