Title :
A high performance 0.5 mu m BiCMOS triple polysilicon technology for 4 Mb fast SRAMs
Author :
Mele, T.C. ; Hayden, J. ; Walczyk, F. ; Lien, M. ; See, Y.C. ; Denning, D. ; Cosentino, S. ; Perera, A.H.
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
A high-performance 0.5 mu m BiCMOS technology has been developed which uses a triple polysilicon process architecture for a 4 Mb fast SRAM class of products. Three layers of polysilicon are used to achieve a compact four transistor cell size that is less than 20 mu m/sup 2/ by creating self-aligned bit-sense and Vss contacts to the four transistor cell. A WSi/sub x/ polycide emitter n-p-n transistor has been implemented with an emitter area of 0.8*2.4 mu m/sup 2/ and peak cutoff frequency (f/sub T/) of 14 GHz. A selectively ion implanted collector has been used to compensate the base channeling tail as well as to increase knee current and f/sub T/, while maintaining a collector to emitter breakdown voltage of 6.5 V. A minimum ECL gate delay of 115 ps has been achieved at a gate current of 400 mu A.<>
Keywords :
BIMOS integrated circuits; SRAM chips; integrated circuit technology; 0.5 micron; 115 ps; 4 Mbit; 400 muA; 6.5 V; BiCMOS; ECL gate delay; WSi/sub x/ polycide emitter; collector to emitter breakdown voltage; compact four transistor cell size; fast SRAM class; gate current; memory IC; n-p-n transistor; polycrystalline Si; selectively ion implanted collector; self-aligned contacts; static RAM; triple polysilicon technology; BiCMOS integrated circuits; Cutoff frequency; Delay; Knee; Random access memory; Tail; Variable structure systems;
Conference_Titel :
Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1990.237063
