Modeling of bias-stress dependent transconductance degradation of submicron MOSFETs

Hot-electron degradation mechanisms for submicron LDD (lightly doped drain) MOSFETs under DC stress are investigated. The rate of device degradation is measured as a function of time under three experimental stress cycles. Two-dimensional device simulators, both Monte Carlo (MC) and drift diffusion (DD) approaches, are used to understand the physical mechanisms and to quantify the experimental results. Unlike other methods, this MC-DD coupled method can directly determine the interfacial defect density profile from the electron energy distribution at the Si-SiO/sub 2/ interface. The results show that the potential barrier height of the Si-SiO/sub 2/ interface should be changed after hole injection and/or defect generation, and also that only a g/sub m/ shift is observed when the interfacial defects are located inside of the LDD.<>