Digital spur mitigation in high-speed block-parallel digital filter realizations

An intuitive procedure for determining the location as well as reducing the effect of digital spurs in block-parallel digital filter realizations is proposed. The method is based on modeling voltage/current waveforms generated by the switching activity of digital clocks in each polyphase component of a blockparallel digital filter as electromagnetic waves travelling over a linear medium. Using superposition, frequency analysis as well as information regarding the area (size) and layout (placement) of the synthesized polyphase filter, the spurs generated at the output of the overall system are modeled as a weighted sum of voltage/current interference waveforms. Digital spur mitigation is achieved by calculating a strategic clock phasing scheme based on the contribution of these weighting coefficients. The technique and examples presented are intended to serve as a high-speed filter realization reference for Digital and DSP ASIC developers.