Investigation of single-event upsets in dynamic logic based flip-flops

We investigate the impact of single-event upsets in dynamic flip-flop circuits, which are more appealing for the design of high-performance microprocessors because of short latency, small area and high clock frequency. Previous work either uses the approaches for static flip-flops to evaluate SEU effects in dynamic flip-flops or overlook the SEU injected during the precharge phase. We re-examine the possible SEU sensitive nodes in dynamic flip-flops and extend the window of vulnerability of dynamic flip-flops. Our simulation results show that the drain nodes of clocked transistors in dynamic flip-flops are also sensitive to SEUs. For a non-hardened dynamic D-flipflop, the last 55.3 % of the precharge phase and the entire evaluation phase are affected by SEUs. However, the upset sensitivity trend is reversed in a hardened dynamic flip-flop.