Complementary III-V heterostructure FETs for low power integrated circuits

Author

Akinwande, A.I. ; Ruden, P.P. ; Grider, D.E. ; Nohava, J.C. ; Nohava, T.E. ; Joslyn, P.D. ; Breezley, J.E.

Author_Institution

Honeywell Inc., Bloomington, MN, USA

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

983

Lastpage

986

Abstract

The authors report on a complementary III-V heterostructure FET (HFET) technology that makes use of high AlAs mole fraction (Al,Ga)As barrier layers to reduce the gate leakage currents of n- and p-channel heterostructure FETs. The subthreshold currents and drain-to-gate leakage currents of p-HFETs are also substantially reduced as a result of the high AlAs mole fraction (AlGa)As barrier layer. A 1024*1 bit complementary HFET SRAM with access times as low as 4.6 ns and power dissipation of 34.8 mW has also been demonstrated using this technology.<>

Keywords

III-V semiconductors; SRAM chips; field effect integrated circuits; integrated circuit technology; leakage currents; (AlGa)As barrier layer; 1024 bit; 34.8 mW; 4.6 ns; HFET SRAM; access times; complementary III-V heterostructure FET; gate leakage currents; high AlAs mole fraction; low power integrated circuits; power dissipation; subthreshold currents; FETs; HEMTs; III-V semiconductor materials; Leakage current; MODFETs; Power dissipation; Random access memory; Subthreshold current;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237075

Filename

237075