A feasibility study of quaternary FPGA designs by implementing Neuron-MOS mechanism

The feasibility of quaternary field programmable gate array (FPGA) is investigated in this work by using standard CMOS technology and ordinary dual-rail of power supply lines. For quaternary signal processing, the basic functional circuits, quaternary memory unit, look-up table (LUT), and framework of FPGA addressing are proposed. Employing the Neuron-MOS mechanism, multi-threshold voltage inverters are designed. A quaternary scheme of static random access memory (SRAM) circuit and LUTs is proposed for FPGA applications on the basis of these inverters. In this manner, a quaternary FPGA is realized in standard CMOS technology and dual-rail power supply. From the circuit simulation results, our designed proof-of-concept four-by-four FPGA achieves all the illustrated functions correctly. The scale of this FPGA can be expanded by implementing our proposed two-dimensional quaternary addressing framework with the reduced cost.