Title :
A novel stacked capacitor cell with dual cell plate for 64 Mb DRAMs
Author :
Arima, H. ; Hachisuka, A. ; Ogawa, T. ; Okudaira, T. ; Okumura, Y. ; Matsui, Y. ; Motonami, K. ; Matsukawa, T. ; Tsubouchi, N.
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
The authors propose a novel stacked capacitor cell with dual cell plate (DCP cell) for 64-Mb DRAMs. The major advantage of this cell is that the dual cell plates completely surround the whole surface of the storage polysilicon, and the storage capacitance of this cell increases significantly compared to the conventional stacked capacitor cell. For a 1.3- mu m/sup 2/ cell, the DCP cell should achieve a storage capacitance of more than 25 fF. The experimental results indicate that the DCP cell can realize the 64-Mb DRAMs and 1.3- mu m/sup 2/ cell area using the 0.3- mu m design rule.<>
Keywords :
DRAM chips; MOS integrated circuits; VLSI; 0.3 micron; 64 Mbit; DCP cell; DRAMs; design rule; dual cell plate; stacked capacitor cell; storage capacitance; storage polysilicon; Capacitance; Capacitors;
Conference_Titel :
Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1990.237115
