A novel CMOS-compatible lateral bipolar transistor for high-speed BiCMOS LSI

Author

Tamba, A. ; Someya, T. ; Sakagami, T. ; Akiyama, N. ; Kobayashi, Yoshiyuki

Author_Institution

Hitachi Ltd., Ibaraki, Japan

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

395

Lastpage

398

Abstract

A CMOS-compatible lateral bipolar transistor suitable for low-cost and high-speed BiCMOS LSIs is proposed, and its high-speed characteristics are demonstrated. The proposed lateral bipolar transistor has a structure analogous to NMOS transistors, which use a source and drain self-aligned structure to form an emitter and collector. The obtained values of h/sub FE/, BV/sub CEO/, R/sub CS/, f/sub TMAX/, and r/sub bb/, are 20, 7 V, 50 Omega , 6.3 GHz, and 450 Omega , respectively. Moreover, delay times of a two-input NAND BiCMOS gate circuit are 0.28 ns when unloaded, and 0.42 ns and 0.53 ns when load capacitances are 1 pF and 2 pF, respectively. These values are equal to those of conventional poly-Si emitter bipolar transistors.<>

Keywords

BIMOS integrated circuits; bipolar transistors; digital integrated circuits; large scale integration; 0.28 to 0.53 ns; CMOS-compatible; delay times; high-speed BiCMOS LSI; high-speed characteristics; lateral bipolar transistor; self-aligned structure; two input NAND gate circuit; BiCMOS integrated circuits; Bipolar transistors; Capacitance; Delay; Iron; MOSFETs;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237148

Filename

237148