DocumentCode :
3317990
Title :
Reliability of laser activated metal fuses in DRAMs
Author :
Arndt, K. ; Narayan, C. ; Brintzinger, A. ; Guthrie, W. ; Lachtrupp, D. ; Mauger, J. ; Glimmer, D. ; Lawn, S. ; Dinkel, B. ; Mitwalsky, A.
Author_Institution :
IBM Microelectron., Hopewell Junction, NY, USA
fYear :
1999
fDate :
1999
Firstpage :
389
Lastpage :
394
Abstract :
Redundancy activation in DRAMs has taken on a critical role in improving and providing high manufacturing yields. Although the concept of redundancy repair is relatively simple, i.e. replacement of faulty cells within a memory array with functional substitutes, the process can be relatively complex. Traditional redundancy repair techniques physically remove the defective cells from the operational circuit by “fusing” predetermined links. The “fusing” process actually removes a portion of the circuit referred to as a link, thereby redefining the address of a defective bit and pointing it to a working bit in the redundant array. In the past, laser fusing was performed on polysilicon materials, primarily gate structures, located in the support area of a memory chip. However, recent developments in back-end processes and the push for cost reduction in DRAM fabrication have motivated us to implement fuses on back-end metal wiring levels. As this migration introduced material and process changes, a qualification plan was instituted to determine the robustness of this new process. This paper examines the reasons to migrate the links to metal levels and outlines the work that was done to qualify this new technology. Fusing characteristics of metal versus polysilicon links are discussed and the effects of fusing variables are described. Finally, data is presented to show that DRAM metal fuses are reliable in large scale manufacturing environments
Keywords :
DRAM chips; electric fuses; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit yield; laser materials processing; maintenance engineering; DRAM fabrication; DRAM metal fuses; DRAMs; back-end metal wiring levels; back-end processes; cost reduction; defective bit address; defective cells; faulty cell replacement; functional substitutes; fuses; fusing process; fusing variables; gate structures; large scale manufacturing environments; laser activated metal fuses; laser fusing; manufacturing yield; memory array; memory chip support area; metal links; operational circuit; polysilicon links; polysilicon materials; qualification plan; redundancy activation; redundancy repair; redundancy repair techniques; reliability; working bit address; Circuit faults; Costs; Fuses; Laser theory; Manufacturing; Optical device fabrication; Optical materials; Random access memory; Redundancy; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Manufacturing Technology Symposium, 1999. Twenty-Fourth IEEE/CPMT
Conference_Location :
Austin, TX
ISSN :
1089-8190
Print_ISBN :
0-7803-5502-4
Type :
conf
DOI :
10.1109/IEMT.1999.804850
Filename :
804850
Link To Document :
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