Carrier confinement in MOS-gated Ge/sub x/Si/sub 1-x//Si heterostructures

Author

Garone, P.M. ; Venkataraman, V. ; Sturm, J.C.

Author_Institution

Dept. of Electr. Eng., Princeton Univ., NJ, USA

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

383

Lastpage

386

Abstract

The confinement of carriers in a MOS-gated Ge/sub x/Si/sub 1-x/ heterostructure is numerically modeled and experimentally confirmed. The structure, which may be useful for improved pMOS device performance, uses a MOS gate to modulate the hole density at a buried Si/Ge/sub x/Si/sub 1-x/ interface. Numerical modeling is used to predict the maximum number of carriers achievable at the interface as a function of the structure design, and clear experimental evidence for such carrier confinement is given. Simulations have shown that it is desirable to use a minimal Si buffer thickness and a maximum Ge fraction to maximize the number of holes confined in the Ge/sub x/Si/sub 1-x/ well, subject to the constraints of surface scattering and processing considerations.<>

Keywords

CMOS integrated circuits; Ge-Si alloys; carrier density; elemental semiconductors; metal-insulator-semiconductor structures; semiconductor device models; semiconductor materials; silicon; CMOS circuits; Ge/sub x/Si/sub 1-x/-Si; MOS-gated heterostructures; buried Si/Ge/sub x/Si/sub 1-x/ interface; carrier confinement; hole density modulation; maximum Ge fraction; minimal Si buffer thickness; modeling; pMOS device; Carrier confinement; MOS devices; Numerical models; Predictive models; Scattering;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237151

Filename

237151