A polycrystalline-Si/sub 1-x/Ge/sub x/-gate CMOS technology

Author

King, T.-J. ; Pfiester, J.R. ; Shott, J.D. ; McVittie, J.P. ; Saraswat, K.C.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

253

Lastpage

256

Abstract

A novel polycrystalline silicon-germanium gate CMOS process has been developed for a submicron CMOS technology. The incorporation of germanium into a heavily doped p-type polycrystalline-silicon (P/sup +/ poly-Si) gate material causes the gate work function to be reduced (more than 300 mV for a 60% Ge material), so that both NMOS and PMOS surface-channel devices may be achieved. In addition, it improves the gate sheet resistance by increasing dopant activation. Poly-Si/sub 1-x/Ge/sub x/ films with Ge mole fractions up to 0.6 were found to be completely compatible with standard VLSI fabrication processes in regard to deposition and patterning techniques, high-temperature chemical and mechanical stability, and electrical stability and uniformity.<>

Keywords

CMOS integrated circuits; Ge-Si alloys; VLSI; integrated circuit technology; CMOS technology; deposition techniques; dopant activation; electrical stability; gate sheet resistance; gate work function; high temperature chemical stability; mechanical stability; patterning techniques; polycrystalline Si/sub 1-x/Ge/sub x/ gates; standard VLSI fabrication processes; standard VLSI processing compatibility; submicron; surface-channel devices; uniformity; work function reduction; CMOS process; CMOS technology; Electric resistance; Germanium silicon alloys; MOS devices; Sheet materials; Silicon germanium; Stability; Surface resistance; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237181

Filename

237181