Design issues for achieving latchup-free, deep trench-isolated, bulk, non-epitaxial, submicron CMOS

The authors describe the improvement of latchup immunity through the use of deep trench-isolation in bulk nonepitaxial CMOS technology. An extensive two-dimensional numerical analysis of a deep trench-isolated, bulk CMOS structure was performed using PISCES-IIB. It is shown that deep trench-isolation, in conjunction with properly designed layout, trench geometry, and doping profiles, can increase the holding voltage significantly. This improvement is due to an increase of the two-dimensional spreading resistance of the conductivity-modulated well and substrate regions in the latched-up state that is caused by the deep trench. By increasing the holding voltage to above the power supply voltage (3.3 V in deep submicron CMOS), latchup-free CMOS can be achieved even in bulk, nonepitaxial substrates.<>