• DocumentCode
    3318674
  • Title

    A flash-TDC hybrid ADC architecture

  • Author

    Yue Xu ; Shabra, Ayman

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Masdar Inst. of Sci. & Technol., Abu Dhabi, United Arab Emirates
  • fYear
    2015
  • fDate
    24-27 May 2015
  • Firstpage
    1270
  • Lastpage
    1273
  • Abstract
    A flash-TDC hybrid ADC architecture is proposed in this paper. The operating principle relies on measuring the impact of the input amplitude on the delay of the comparators in the flash. TDCs capture this timing information, which is mapped to an output digital code using simple digital logic to provide additional bits of resolution.
  • Keywords
    analogue-digital conversion; comparators (circuits); delays; comparator delay; flash TDC; hybrid ADC architecture; input amplitude; timing information; Binary codes; Clocks; Computer architecture; Jitter; Power demand; Threshold voltage; Timing; analog-digital conversion; time-to-digital converter; two-step ADC;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
  • Conference_Location
    Lisbon
  • Type

    conf

  • DOI
    10.1109/ISCAS.2015.7168872
  • Filename
    7168872
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3318674