Title :
A flash-TDC hybrid ADC architecture
Author :
Yue Xu ; Shabra, Ayman
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Masdar Inst. of Sci. & Technol., Abu Dhabi, United Arab Emirates
Abstract :
A flash-TDC hybrid ADC architecture is proposed in this paper. The operating principle relies on measuring the impact of the input amplitude on the delay of the comparators in the flash. TDCs capture this timing information, which is mapped to an output digital code using simple digital logic to provide additional bits of resolution.
Keywords :
analogue-digital conversion; comparators (circuits); delays; comparator delay; flash TDC; hybrid ADC architecture; input amplitude; timing information; Binary codes; Clocks; Computer architecture; Jitter; Power demand; Threshold voltage; Timing; analog-digital conversion; time-to-digital converter; two-step ADC;
Conference_Titel :
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location :
Lisbon
DOI :
10.1109/ISCAS.2015.7168872
