Lossless data compression programmable hardware for high-speed data networks

This paper presents a high-performance application specific architecture for real time lossless data compression, which enables data throughputs over 1.5 Gbits/s compression and decompression using contemporary low-cost re-programmable FPGA technology. The implementation is embedded into a PCI-based system and tested at speed using a PC as the host computer.. A single FPGA is used to map all the functions in the system including the compression and decompressor cores, DMA logic, control logic and Master/Target PCI core. The independent compression and decompression channels enable a combined compression and decompression performance over 3 Gbits/s and robust self-checking hardware where each compress block can be automatically decompressed to defect hardware failures or errors introduced by the communication channel.