DocumentCode :
3318763
Title :
A multiplier-less FPGA core for image algebra neighbourhood operations
Author :
Benkrid, K.
Author_Institution :
Sch. of Comput. Sci., Queen´´s Univ., Belfast, UK
fYear :
2002
fDate :
16-18 Dec. 2002
Firstpage :
294
Lastpage :
297
Abstract :
This paper presents the design and implementation of a high-level generator of optimised FPGA configurations for Image Algebra (IA) neighbourhood operations. These configurations are parameterised and scaleable in terms of the IA operation itself the window size, the window coefficients, the input pixel word length and the image size. The window coefficients of the neighbourhood operations are represented as sum/subtract of power of twos in Canonical Signed Digit (CSD) representation, which means that the usually costly multiplication operation can be easily implemented using a small number of simple shift-and-add operations, leading to considerable hardware savings. EDIF netlists are generated automatically from high-level descriptions of the IA operations in ∼1 sec. These are specifically optimised for Xilinx XC4000 chips, although implementations for other targets can also be easily realised.
Keywords :
digital arithmetic; electronic data interchange; field programmable gate arrays; high level synthesis; EDIF netlists; Xilinx XC4000 chips; canonical signed digit representation; high-level descriptions; high-level generator; image algebra neighbourhood operations; image size; input pixel word length; multiplier-less FPGA core; shift-and-add operations; window coefficients; window size; Acceleration; Algebra; Computer applications; Computer science; Convolution; Field programmable gate arrays; Hardware; Image processing; Parallel processing; Pixel;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on
Print_ISBN :
0-7803-7574-2
Type :
conf
DOI :
10.1109/FPT.2002.1188695
Filename :
1188695
Link To Document :
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