Title :
A 5 volt only 16M bit flash EEPROM cell with a simple stacked gate structure
Author :
Ajika, N. ; Ohi, M. ; Arima, H. ; Matsukawa, T. ; Tsubouchi, N.
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A 3.6 mu m/sup 2/ 5 V only 16 Mb flash EEPROM cell was obtained using a simple stacked gate structure and a conventional 0.6 mu m CMOS process. A single 5 V power supply operation of the simple stacked gate cell was realized by optimizing the well impurity concentration and the drain structure and using a gate negative biased erasing operation. It is also shown that the gate negative biased erasing operation mode is very effective in improving the cell endurance characteristics.<>
Keywords :
CMOS integrated circuits; EPROM; integrated memory circuits; 0.6 micron; 16 Mbit; 5 V; CMOS process; cell endurance characteristics; drain structure; flash EEPROM cell; gate negative biased erasing operation; single 5 V power supply operation; stacked gate structure; well impurity concentration; CMOS process; EPROM; Impurities; Power supplies;
Conference_Titel :
Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1990.237213
