DocumentCode :
3318863
Title :
Efficient 4-input LUTs FPGA implementation of combinatorial multiplier over canonical base GF(16)
Author :
Tomashau, Valeri
fYear :
2002
fDate :
16-18 Dec. 2002
Firstpage :
318
Lastpage :
321
Abstract :
Finite field arithmetic is the basis of some cryptographic and error correction algorithms. The performance of a corresponding hardware depends on the efficiency of the finite field arithmetic implementation. A good-quality finite field multiplier is needed first, since multiplication is an often-used and time consuming operation. Because FPGAs differ considerably in structure from other integrated circuits, the finite field multiplier designs, which are optimized for VLSI implementation, do not perform well on FPGAs. In this paper, some structures of a completely combinatorial GF(16) multiplier, based on 4-input LUTs and some other resources of the Xilinx FPGA, have been proposed. As a result, some improvement in area and time has been achieved by comparison with previous designs.
Keywords :
Galois fields; combinational circuits; digital arithmetic; field programmable gate arrays; logic design; table lookup; Galois fields; LUT-based FPGA; canonical base GF(16) multiplier; combinatorial multiplier; cryptographic algorithms; error correction algorithms; finite field arithmetic; finite field multiplier; multiplication; Arithmetic; Boolean functions; Circuits; Cryptography; Equations; Error correction; Field programmable gate arrays; Galois fields; Hardware; Table lookup;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on
Print_ISBN :
0-7803-7574-2
Type :
conf
DOI :
10.1109/FPT.2002.1188701
Filename :
1188701
Link To Document :
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