Efficient 4-input LUTs FPGA implementation of combinatorial multiplier over canonical base GF(16)

Finite field arithmetic is the basis of some cryptographic and error correction algorithms. The performance of a corresponding hardware depends on the efficiency of the finite field arithmetic implementation. A good-quality finite field multiplier is needed first, since multiplication is an often-used and time consuming operation. Because FPGAs differ considerably in structure from other integrated circuits, the finite field multiplier designs, which are optimized for VLSI implementation, do not perform well on FPGAs. In this paper, some structures of a completely combinatorial GF(16) multiplier, based on 4-input LUTs and some other resources of the Xilinx FPGA, have been proposed. As a result, some improvement in area and time has been achieved by comparison with previous designs.