Title :
Process and device technologies for 16 Mbit EPROMs with large-tilt-angle implanted p-pocket cell
Author :
Ohshima, Y. ; Mori, S. ; Kaneko, Y. ; Sakagami, E. ; Arai, N. ; Hosokawa, N. ; Yoshikawa, K.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
A reliable high-performance process and device technologies for the fabrication of a 0.6 mu m 16 Mbit CMOS EPROM have been developed. A novel cell structure called a LAP cell is proposed, which yields stable high performance in the 0.6 mu m regime. The important processes and device technologies are a large-tilt-angle implanted p-pocket (LAP) cell structure with 0.6 mu m gate length, a self-aligned source (SAS) technology, a poly-Si plugged-contact technology for CMOS devices via a novel multistep poly-Si deposition method, and a 0.8 mu m poly-Si shield isolation structure for high voltage circuits. It is noted that these technologies together with advanced lithography techniques will be sufficient for the manufacture of future 64 Mbit EPROMs and beyond.<>
Keywords :
CMOS integrated circuits; EPROM; VLSI; integrated circuit technology; integrated memory circuits; 0.6 micron; 16 Mbit; CMOS; EPROMs; LAP cell; device technologies; gate length; large-tilt-angle implanted p-pocket cell; lithography techniques; multistep polysilicon deposition method; polysilicon plugged-contact technology; polysilicon shield isolation structure; self-aligned source; CMOS process; CMOS technology; Circuits; EPROM; Fabrication; Isolation technology; Lithography; Manufacturing; Synthetic aperture sonar; Voltage;
Conference_Titel :
Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1990.237218
