A novel memory cell using flash array contactless EPROM (FACE) technology

Author

Woo, B.J. ; Ong, T.C. ; Fazio, A. ; Park, C. ; Atwood, G. ; Holler, M. ; Tam, S. ; Lai, S.

Author_Institution

Intel Corp., Santa Clara, CA, USA

fYear

1990

fDate

9-12 Dec. 1990

Firstpage

91

Lastpage

94

Abstract

A single transistor flash memory cell which utilizes channel hot electron injection for programming and Fowler-Nordheim tunneling for erase is described. This flash memory technology uses a buried N/sup +/ bitline to connect the memory transistors rather than metal and contacts. Elimination of contacts results in a 45% cell area shrink of the conventional ETOX cell (based on 1.0 mu m design rules). A 4.48 mu m/sup 2/ cell area is also realized by using a 0.8 mu m technology. In addition to this cell scalability, the diffusion corner induced erase threshold bimodality can be reduced due to the intrinsic stripe geometries in the memory array. Furthermore, this contact/metal related layout rules can be relaxed, which allows this contactless approach to be extended to future generations without requiring complicated contact processing. Hence, the flash array contactless EPROM (FACE) technology lends itself to a very compact cell as well as a more manufacturable process.<>

Keywords

EPROM; hot carriers; integrated memory circuits; tunnelling; 0.8 micron; 1.0 micron; ETOX cell; FACE technology; Fowler-Nordheim tunneling; buried N/sup +/ bitline; cell scalability; channel hot electron injection; diffusion corner; flash array contactless EPROM; intrinsic stripe geometries; memory cell; threshold bimodality; Channel hot electron injection; EPROM; Flash memory; Flash memory cells; Geometry; Manufacturing processes; Scalability; Transistors; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1990.237219

Filename

237219