VLSI implementation of 16-point DCT for H.265/HEVC using walsh hadamard transform and lifting scheme

Author

Ahmed, Ashfaq ; Awais, Muhammad ; Maurizio, Martina ; Masera, Guido

Author_Institution

Dept. of Electron., Politec. di Torino, Torino, Italy

fYear

2011

fDate

22-24 Dec. 2011

Firstpage

144

Lastpage

148

Abstract

In this paper, a fast 16-point DCT is implemented using a multiplier-less architecture. The 16-point DCT matrix is decomposed into sparse sub-matrices in order to reduce the multiplications and finally the multiplications are completely eliminated using the lifting scheme. Therefore, the computational complexity of the architecture is much lower than the direct implementation of 16-point DCT. In software implementation, 45 dB of PSNR is achieved for the “Lena” image. The VLSI implementation has been carried out for a 90-nm standard cell technology at a clock frequency of 150 MHz.

Keywords

Hadamard transforms; Walsh functions; computational complexity; data compression; discrete cosine transforms; sparse matrices; video coding; 16-point DCT matrix; H.265-HEVC; Lena image; PSNR; VLSI implementation; Walsh Hadamard transform; computational complexity; frequency 150 MHz; lifting scheme; size 90 nm; sparse submatrices; standard cell technology; Discrete cosine transforms; Registers; Discrete Time Cosine Transform (DCT); High Efficiency Video Coding (HEVC); PSNR (Peak Signal to Noise Ratio); WHT (Walsh Hadamard Transform);

fLanguage

English

Publisher

ieee

Conference_Titel

Multitopic Conference (INMIC), 2011 IEEE 14th International

Conference_Location

Karachi

Print_ISBN

978-1-4577-0654-7

Type

conf

DOI

10.1109/INMIC.2011.6151460

Filename

6151460