An efficient architecture for an improved watershed algorithm and its FPGA implementation

Author

Rambabu, Ch ; Chakrabarti, I. ; Mahanta, A.

Author_Institution

ECE Dept., Indian Inst. of Technol., Guwahati, India

fYear

2002

fDate

16-18 Dec. 2002

Firstpage

370

Lastpage

373

Abstract

This paper proposes a fast watershed algorithm derived from Meyer´s simulated flooding based algorithm. The parallel processing adopted in conditional neighborhood comparisons for processing 3×3 pixels in one process leads to reduced computational complexity compared to Meyer´s algorithm. The proposed algorithm has been implemented in an Xilinx FPGA environment.

Keywords

computational complexity; digital signal processing chips; field programmable gate arrays; image segmentation; parallel algorithms; parallel architectures; VLSI architectures; Xilinx FPGA environment; computational complexity reduction; conditional neighborhood comparisons; fast watershed algorithm; parallel processing; simulated flooding based algorithm; Computational complexity; Computational modeling; Computer architecture; Field programmable gate arrays; Floods; Hardware; Labeling; Pixel; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on

Print_ISBN

0-7803-7574-2

Type

conf

DOI

10.1109/FPT.2002.1188713

Filename

1188713

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3319081