DocumentCode :
3319105
Title :
RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications
Author :
Parthasarathy, Shyam ; Trivedi, Amit ; Sirohi, Saurabh ; Groves, Robert ; Olsen, Michael ; Chauhan, Yogesh S. ; Carroll, Michael ; Kerr, Dan ; Tombak, Ali ; Mason, Phil
fYear :
2010
fDate :
3-7 Jan. 2010
Firstpage :
194
Lastpage :
199
Abstract :
A single-pole double-throw novel switch device in 0.18 ¿m SOI complementary metal-oxide semiconductor (CMOS) process is developed for 0.9 Ghz wireless GSM systems. The layout of the device is optimized keeping in mind the parameters of interest for the RF switch. A subcircuit model, with the standard surface potential (PSP) model as the intrinsic FET model along with the parasitic elements is built to predict the Ron and Coff of the switch. The measured data agrees well with the model. The eight FET stacked switch achieved an Ron of 2.5 ohms and an Coff of 180 fF.
Keywords :
CMOS integrated circuits; cellular radio; field effect transistor switches; integrated circuit layout; integrated circuit modelling; radiofrequency integrated circuits; silicon-on-insulator; surface potential; CMOS; FET stacked switch; RF SOI switch FET design; RF SOI switch FET modeling; SOI complementary metal-oxide semiconductor process; Si; capacitance 180 fF; device layout; frequency 0.9 GHz; intrinsic FET model; parasitic element; resistance 2.5 ohm; single-pole double-throw switch device; size 0.18 mum; standard surface potential model; subcircuit model; wireless GSM systems; CMOS process; CMOS technology; Communication switching; FETs; GSM; Predictive models; Radio frequency; Semiconductor device modeling; Switches; Voltage; GSM; RF Switch; SPDT;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2010. VLSID '10. 23rd International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Print_ISBN :
978-1-4244-5541-6
Type :
conf
DOI :
10.1109/VLSI.Design.2010.64
Filename :
5401194
Link To Document :
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