Title : 
A memory-efficient NoC system for OpenCL many-core platform
         
        
            Author : 
Chien-Hsuan Yen ; Chung-Ho Chen ; Kuan-Chung Chen
         
        
            Author_Institution : 
Inst. of Comput. & Commun. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
         
        
        
        
        
        
            Abstract : 
We present a memory-efficient NoC system for OpenCL many-core platforms. By offloading the OpenCL kernel programs into the many-core processor, we reveal that the memory contention overheads have dramatically increased with the scaling of the system, resulting to the poor performance scalability of the many-core system. We explore a memory-efficient NoC system design which includes a mesh network, a hybrid network interface for packet composition and decomposition, and a memory controller with access scheduling capability. Our experimental results show that a simple memory access scheduling and caching approach can easily boost the performance of the NoC and memory system up to 20 percent by eliminating the memory controller contention problem.
         
        
            Keywords : 
DRAM chips; network-on-chip; OpenCL many-core platform; access scheduling capability; hybrid network interface; many-core processor; memory access scheduling; memory contention overheads; memory controller; memory-efficient NoC system; mesh network; Bandwidth; Memory management; Network interfaces; Random access memory; Scalability; DRAM access scheduling; Mesh NoC; OpenCL; full system simulation; many-core system;
         
        
        
        
            Conference_Titel : 
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
         
        
            Conference_Location : 
Lisbon
         
        
        
            DOI : 
10.1109/ISCAS.2015.7168901