Analysis and optimization for dynamic read stability in 28nm SRAM bitcells

Author

Elthakeb, Ahmed T. ; Haine, Thomas ; Flandre, Denis ; Ismail, Yehea ; Abd Elhamid, Hamdy ; Bol, David

Author_Institution

Center for Nano-Electron. & Devices (CND), American Univ. in Cairo (AUC), Cairo, Egypt

fYear

2015

fDate

24-27 May 2015

Firstpage

1414

Lastpage

1417

Abstract

The importance of the dynamic analysis for SRAM operation increases as a result of shrinking access cycle time, voltage scaling and increased process variations. In this paper, quantitative study of the dynamic read noise margin (DNM) is introduced showing the evolution from the static read noise margin (SNM) to DNM through cumulative dynamic effects in 28nm FDSOI. The impact of parasitic capacitances on the DNM is further analyzed. Finally, we show that by sizing for a 150-mV DNM instead of a 150-mV SNM and by inserting two 0.5fF extra caps in the bitcell allows reducing the pull-down NMOS width by a factor 3.5×.

Keywords

SRAM chips; circuit stability; integrated circuit noise; silicon-on-insulator; DNM; FDSOI; SNM; SRAM bitcell; cumulative dynamic effect; dynamic read noise margin; dynamic read stability; fully depleted silicon-on-insulator; n-type metal oxide semiconductor field effect transistor; parasitic capacitance; process variation; pull-down NMOS; shrinking access cycle time; size 28 nm; static random access memory; static read noise margin; voltage 150 mV; voltage scaling; Capacitance; Circuit stability; Couplings; Noise; Random access memory; Stability analysis; Transient analysis; 6T SRAM; Cell sizing; Dynamic behavior; FD SOI; Read Noise Margin; parasitic capacitances;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2015 IEEE International Symposium on

Conference_Location

Lisbon

Type

conf

DOI

10.1109/ISCAS.2015.7168908

Filename

7168908