Design and implementation of simulator for AOS high-speed payload multiplexer

A small simulator for AOS high-speed payload multiplexer is designed and implemented based on the idea of satellite hierarchical test, which will be used in the test for satellite data transmission subsystem. The simulator uses the FPGA as control center, including multi-input and multi-output LVDS and RS422 interfaces. It caches the received payload data using the large-capacity SRAM dual caching technology, selects data downlink channel and downlink rate which both can be configured, uses a virtual channel (VC) scheduling algorithm based on the Consultative Committee for Space Data Systems (CCSDS) Advanced Orbiting Systems (AOS) data link protocol to make many kinds of VCs multiplexing physical downlink channel effectively. Finally multi-channel downlinks the payload data timely and correctly. The closed-loop path test results from the data source to the data receiving terminal show that the simulator can meet the technical requirements of the real satellite payload data high-speed multiplexer.