• DocumentCode
    3319359
  • Title

    Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors

  • Author

    Saripalli, Vinay ; Narayanan, Vijaykrishnan ; Datta, Suman

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
  • fYear
    2010
  • fDate
    3-7 Jan. 2010
  • Firstpage
    399
  • Lastpage
    404
  • Abstract
    This paper presents single electron transistor (SET) devices operating at room temperature as an attractive option to implement low energy consumption circuits with low-to-moderate performance requirements. Currently, such circuits are implemented using CMOS technologies operating at low supply voltages. CMOS is usually leakage dominated at such a low voltage regime and various optimizations are necessary to design low energy circuits. By discussing the energy-delay trade-offs for SET devices and comparing them to those of contemporary CMOS technology, we present an argument that SET devices may be more favorable compared to CMOS from the energy and delay standpoints at low supply voltages.
  • Keywords
    CMOS integrated circuits; delays; low-power electronics; single electron transistors; CMOS technologies; SET; energy circuits design; energy consumption circuits; energy-delay behavior; energy-delay trade-offs; single electron transistors; temperature 293 K to 298 K; CMOS technology; Dynamic voltage scaling; Energy consumption; Logic circuits; Low voltage; Nanoscale devices; Parasitic capacitance; Single electron transistors; Switches; Temperature; Energy Efficient; Energy-Delay Trade-Off; Single Electron Transistor;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2010. VLSID '10. 23rd International Conference on
  • Conference_Location
    Bangalore
  • ISSN
    1063-9667
  • Print_ISBN
    978-1-4244-5541-6
  • Type

    conf

  • DOI
    10.1109/VLSI.Design.2010.48
  • Filename
    5401213