DocumentCode :
3319389
Title :
On Minimization of Test Application Time for RAS
Author :
Adiga, Raghavendra ; Arpit, Gandhi ; Singh, Virendra ; Saluja, Kewal K. ; Fujiwara, Hideo ; Singh, Adit D.
Author_Institution :
Indian Inst. of Sci., Bangalore, India
fYear :
2010
fDate :
3-7 Jan. 2010
Firstpage :
393
Lastpage :
398
Abstract :
Conventional random access scan (RAS) for testing has lower test application time, low power dissipation, and low test data volume compared to standard serial scan chain based design. In this paper, we present two cluster based techniques, namely, serial input random access scan and variable word length random access scan to reduce test application time even further by exploiting the parallelism among the clusters and performing write operations on multiple bits. Experimental results on benchmarks circuits show on an average 2-3 times speed up in test write time and average 60% reduction in write test data volume.
Keywords :
VLSI; integrated circuit testing; VLSI testing; cluster based techniques; conventional RAS; low power dissipation; random access scan; serial input random access scan; test application time; test data volume; variable word length random access scan; Built-in self-test; Circuit testing; Clocks; Costs; Design for testability; Flip-flops; Power dissipation; Routing; Very large scale integration; Writing; DFT; Random Access Scan (RAS); Scan Design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2010. VLSID '10. 23rd International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Print_ISBN :
978-1-4244-5541-6
Type :
conf
DOI :
10.1109/VLSI.Design.2010.61
Filename :
5401216
Link To Document :
بازگشت