Optical Lithography Simulation with Focus Variation using Wavelet Transform

Printed image on silicon wafer differs from layout due to optical diffraction. Optical proximity correction (OPC) is a layout distortion technique to improve printed image. During manufacturing, parameters such as focus, dose and resist thickness may vary within tolerance margins. These factors contribute to additional distortion of expected printed shape, not addressed directly by OPC. To ensure a robust IC, a process window consideration is extremely important while running lithography simulations as we scale the technology even further, where the sensitivity of patterns printed on silicon to process variations is very high. Optical Lithography simulation has always been an important link in the chain for Design for manufacturability (DFM) and a lot of research has been put into making it faster and more accurate. However, being a compute intensive process, speeding up litho simulation without significant compromise in accuracy has always been tricky. In this paper we propose a new method to approximate litho simulation based on wavelet transform as opposed to the traditional method employed and we validate the speed and accuracy of our simulator by comparing our results with those of a popular commercial Lithography simulator considering focus variations. While our simulator suffers from an RMS error of < 6%, the major gains are (1) an increase in simulation speed of > 20X and (2) the ability to simulate very large circuit masks where the commercial software fails and direct incorporation of (3) manufacturing process variation. This allows litho simulation against multiple manufacturing process corners, which in turn helps in producing robust design.