A current-draining folded up-conversion mixer and pre-amplifier stage in a CMOS technology for IEEE 802.11a WPAN applications

Author

Ramiah, H. ; Zainal, T.

Author_Institution

Sch. of Electr. & Electron. Eng., Univ. Sains Malaysia, Penang, Malaysia

fYear

2005

fDate

30 Nov.-2 Dec. 2005

Firstpage

168

Lastpage

171

Abstract

This paper describes a 3.5-GHz up-conversion mixer core utilized in a two step transmitter architecture in compliant with IEEE 802.11a WPAN application. The design is based on current-draining folded architecture. The main advantage of the introduced mixer topology is: high linearity and moderate conversion power gain. The mixer is designed in a 0.18-μm CMOS technology, operating from 1.8-V power supply. The integrated up-converter and preamplifier consumes 5 mA and 22 mA of current respectively from 1.8-V supply and shows 4.73-dBm OIP3 (-1.74-dBm IIP3) and -9.41-dBm P1 dB with 5.65 dBm of conversion power gain.

Keywords

CMOS integrated circuits; local area networks; mixers (circuits); network topology; personal area networks; preamplifiers; 1.8 V; 22 mA; 3.5 GHz; 5 mA; CMOS technology; IEEE 802.11a WPAN applications; current-draining folded architecture; current-draining folded up-conversion mixer; integrated up-converter; mixer topology; preamplifier stage; two step transmitter architecture; CMOS technology; Circuits; Design engineering; Frequency; Linearity; Low voltage; OFDM modulation; Transconductors; Transmitters; Voltage-controlled oscillators; CMOS mixers; current draining; folded up-conversion mixers; low voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio-Frequency Integration Technology: Integrated Circuits for Wideband Communication and Wireless Sensor Networks, 2005. Proceedings. 2005 IEEE International Workshop on

Print_ISBN

0-7803-9372-4

Type

conf

DOI

10.1109/RFIT.2005.1598902

Filename

1598902