Design and analysis of a high-speed comparator

Author

Jun, Gu ; Yong, Lian ; Bo, Shi

Author_Institution

Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore

fYear

2005

fDate

30 Nov.-2 Dec. 2005

Firstpage

215

Lastpage

218

Abstract

This paper presents the design and analysis of an ultra high-speed bipolar comparator based on master-slave architecture. The comparator can be used for very high speed data converters design. Master-slave structure is used to improve metastability behavior and reduce minimum differential input voltage. Implemented in a 0.35-μm SiGe BiCMOS process, the comparator consumes approximately 70 mW with sampling speed of 16 GHz and resolvable minimum input voltage of 8 mV peak-to-peak.

Keywords

BiCMOS integrated circuits; analogue-digital conversion; bipolar integrated circuits; comparators (circuits); germanium alloys; silicon alloys; 16 GHz; 70 mW; 8 mV; BiCMOS process; high speed data converters design; master-slave architecture; metastability behavior; minimum differential input voltage reduction; ultrahigh-speed bipolar comparator; Analog-digital conversion; BiCMOS integrated circuits; Clocks; Master-slave; Metastasis; Power dissipation; Preamplifiers; Sampling methods; Tracking loops; Voltage; High-speed comparator design; analog-to-digital converters; bipolar IC design; flash ADC design;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio-Frequency Integration Technology: Integrated Circuits for Wideband Communication and Wireless Sensor Networks, 2005. Proceedings. 2005 IEEE International Workshop on

Print_ISBN

0-7803-9372-4

Type

conf

DOI

10.1109/RFIT.2005.1598914

Filename

1598914