DocumentCode :
3319918
Title :
Design of Phase Locked-Loop for Very Slow Sine-Wave Signals
Author :
Haze, J. ; Vrba, R. ; Prokop, R.
Author_Institution :
Dept. of Microelectron., Univ. of Technol., Brno
fYear :
2008
fDate :
13-18 April 2008
Firstpage :
329
Lastpage :
333
Abstract :
The paper describes the design procedure of phase-locked loop (PLL). This PLL is used in measurement chain with pressure sensor and band-pass sigma-delta modulator to synchronize the input slow sine-wave signal from sensor with driving clock (signal from PLL) of modulator. The frequency of input sine-wave signal is 15,625 kHz. The PLL output (voltage controlled-oscillator) has to generate 62,5 kHz square driving signal. The paper shows design process of most important stages in CMOS 0.7 mum AMIS technology and it also presents simulation results, which confirm the design process of these blocks.
Keywords :
CMOS integrated circuits; phase locked loops; pressure sensors; sigma-delta modulation; voltage-controlled oscillators; CMOS AMIS technology; PLL; band-pass sigma-delta modulator; phase locked-loop design; pressure sensor; slow sine-wave signals; voltage controlled-oscillator; CMOS process; Clocks; Delta-sigma modulation; Frequency synchronization; Phase locked loops; Pressure measurement; Process design; Signal design; Signal generators; Voltage control; phase locked-loop; sine wave signal;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Systems, 2008. ICONS 08. Third International Conference on
Conference_Location :
Cancun
Print_ISBN :
978-0-7695-3105-2
Electronic_ISBN :
978-0-7695-3105-2
Type :
conf
DOI :
10.1109/ICONS.2008.70
Filename :
4497145
Link To Document :
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