A low-power pulse position modulation transceiver

This paper presents a design of a pulse position modulation (PPM) transceiver. The proposed PPM receiver does not need clock forwarding or a reference clock. Moreover, the proposed receiver is implemented with a phase-locked loop and only a sampling flip-flop because need for a frequency detection circuit is eliminated. The duty-cycle distortions of the TX and RX clocks are tolerated without duty-cycle error correction. As a result, wire count and power consumption are minimized in the proposed transceiver. The proposed PPM transceiver is fabricated in 65-nm low-power CMOS technology, and dissipates 7 mW at 800-Mbps data rate. The proposed transceiver occupies a silicon area of 1.2 mm². RMS jitter of the RX recovered clock is measured to 19.7 ps with PRBS-7 data pattern. The overall transceiver achieves an error-free operation.