• DocumentCode
    3321163
  • Title

    Multiprocessor memory reference generation using Cerberus

  • Author

    Rothman, Jeffrey B. ; Smith, Alan Jay

  • Author_Institution
    Dept. of Comput. Sci., California Univ., Berkeley, CA, USA
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    278
  • Lastpage
    287
  • Abstract
    Presents Cerberus, an efficient system for simulating the execution of shared-memory, multiprocessor programs on a uniprocessor workstation. Using EDS (execution-driven simulation), it generates address traces which can be used to drive cache simulations on-the-fly, eliminating the large disk space requirements needed by trace files. It is fast because it links the program to be traced together with the cache or statistics gathering tool into a single executable, which eliminates the context switching needed by communicating processes. It is flexible because it has a simple interface which allows users to easily add any kind of module to use the generated trace information. It compares favorably to other existing tracers; it runs on a commonly available workstation and it is accurate, allowing cycle-by-cycle interactions between the simulated processors. The resulting slowdown from Cerberus is approximately 31 in uniprocessor mode and 45-50 in multiprocessor mode, relative to the workloads run natively on the same machines. We demonstrate that EDS uses only 5% of the total execution cycles when combined with a cache simulator, and we show that EDS is just as efficient as using trace-driven simulation
  • Keywords
    cache storage; multiprocessing programs; program diagnostics; shared memory systems; statistics; storage allocation; virtual machines; Cerberus; address traces; cache simulations; cycle-by-cycle interactions; efficiency; execution cycles; execution-driven simulation; multiprocessor memory reference generation; shared-memory multiprocessor program execution simulation; slowdown; software modules; statistics gathering tool; uniprocessor workstation; user interface; Computational modeling; Computer architecture; Computer science; Computer simulation; Context; Electronic switching systems; Hardware; Microelectronics; Read only memory; Statistics;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 1999. Proceedings. 7th International Symposium on
  • Conference_Location
    College Park, MD
  • Print_ISBN
    0-7695-0381-0
  • Type

    conf

  • DOI
    10.1109/MASCOT.1999.805065
  • Filename
    805065