• DocumentCode
    3321262
  • Title

    Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array

  • Author

    Honkote, Vinayak ; Taskin, Baris

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Drexel Univ., Philadelphia, PA, USA
  • fYear
    2010
  • fDate
    3-7 Jan. 2010
  • Firstpage
    218
  • Lastpage
    223
  • Abstract
    The high frequency of the rotary clocking technology is often susceptible to implementation parameters such as the variation in the total capacitive load distribution between the rings. SPICE simulations performed on the rotary rings with unbalanced capacitive load distribution show a 30.31% variation in the simulated frequencies across the rings. To address this problem, two novel methodologies called OCLB and SOCLB, are formulated for the optimal capacitive load balancing and sub-optimal capacitive load balancing with minimized wirelength, respectively. SPICE simulations performed with OCLB show 0.30% variation in the simulated frequencies across the rings. Further, SOCLB results in an average wirelength improvement of 69.24% over OCLB with a relatively balanced capacitive load distribution. SPICE simulations performed with SOCLB show 2.40% variation in the simulated frequencies across the rings, improved significantly over the 30.31% variation of the unbalanced case.
  • Keywords
    SPICE; clocks; digital integrated circuits; integrated circuit design; SPICE simulations; optimal capacitive load balancing; rotary clocking technology; rotary oscillatory array; sub-optimal capacitive load balancing; unbalanced capacitive load distribution; Analytical models; Circuit simulation; Clocks; Computational modeling; Frequency; Load management; Oscillators; Power dissipation; Resonance; SPICE; Capacitive load balancing; Low power; Optimization; Resonant clocking; Spice;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2010. VLSID '10. 23rd International Conference on
  • Conference_Location
    Bangalore
  • ISSN
    1063-9667
  • Print_ISBN
    978-1-4244-5541-6
  • Type

    conf

  • DOI
    10.1109/VLSI.Design.2010.71
  • Filename
    5401322