DocumentCode
3321302
Title
A New Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications
Author
Sithanandam, Radhakrishnan ; Kumar, M. Jagadesh
Author_Institution
Dept. of Electr. Eng., Indian Inst. of Technol. Delhi, New Delhi, India
fYear
2010
fDate
3-7 Jan. 2010
Firstpage
230
Lastpage
234
Abstract
In this paper, we propose a new hetero-material stepped gate (HSG) SOI LDMOS in which the gate is divided into three sections - an n+ gate sandwiched between two p+ gates and the gate oxide thickness increases from source to drain. This new device structure improves the inversion layer charge density in the channel, results in uniform electric field distribution in the drift region and reduces the gate to drain capacitance. Using two-dimensional simulation, the HSG LDMOS is designed and compared with the conventional LDMOS. We demonstrate that the proposed device exhibits 28% improvement in breakdown voltage, 32% reduction in on-resistance, 13% improvement in transconductance, 9% reduction in gate to drain charge and 38% reduction in switching delay. HSG LDMOS may be effectively deployed in RF power amplifier applications.
Keywords
MOSFET; capacitance; electric resistance; inversion layers; power amplifiers; semiconductor device breakdown; semiconductor device models; silicon-on-insulator; RF power amplifier; Si; breakdown voltage; device structure; drift region electric field distribution; gate oxide thickness; gate to drain capacitance; gate to drain charge; heteromaterial stepped gate SOI LDMOS; inversion layer charge density; laterally double diffused metal oxide semiconductor; n+ gate; on-resistance; p+ gates; radiofrequency amplifier; silicon on insulator; switching delay; transconductance; two-dimensional simulation; CMOS technology; Delay; Etching; Fabrication; Isolation technology; Power amplifiers; Radio frequency; Radiofrequency amplifiers; Silicon on insulator technology; Transconductance; LDMOS; SOI; breakdown voltage; on-resistance; transconductance;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2010. VLSID '10. 23rd International Conference on
Conference_Location
Bangalore
ISSN
1063-9667
Print_ISBN
978-1-4244-5541-6
Type
conf
DOI
10.1109/VLSI.Design.2010.65
Filename
5401324
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