Analog Circuit Design Methodologies to Improve Negative-Bias Temperature Instability Degradation

Negative-bias temperature instability (NBTI) has become one of the major sources of performance degradation in scaled PMOS devices, affecting the threshold voltages of the devices, which in turn affects yield and lifetime reliability as well as the power consumption and performance of circuits. Hence, it has become necessary to understand and reduce the impact of NBTI on PMOS devices. This paper identifies the characteristic of PMOS stresses in differential pairs. Two techniques are proposed for improving performance in the face of NBTI-switching the inputs of the differential transistors, and body-bias modulation based on offset in the common mode output. Simulation results are described. Both techniques bring the offset voltage to a very low value. The body biasing technique improves the output characteristic transition window width from 0.11 V to 0.02 V.