An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops

In this paper, an improved high resolution CMOS timing generator using array of digital delay lock loops is presented. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub gate delay resolution to be implemented. The proposed delay lock loops use novel start controlled dual phase and frequency detector along with a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge and the trailing edge of an input clock reference. The delay lock loop locks to both the leading and trailing clock edges as the start controlled dual phase and frequency detector along with charge pump convert the phase difference into voltage, which greatly reduces the timing jitter. In the start controlled dual phase and frequency detector, the start-controlled circuit is used to provide a precise output without the locking problem. The results show that the total delay time between the input and the output of the DLL (delay lock loop) is one clock cycle and all of the delay cells provide precise output without false locking or harmonic locking. Test results show a timing jitter of less than 5 pS for the DLL circuit and has very low phase sensitivity errors. The timing generator implemented as an array of delay locked loops has exponentially reduced the locking time as well avoids false locking or harmonic locking. An experimental proto type was simulated using 0.35 ¿ technology with a supply voltage of 3.3 V.