A methodology for evaluating the performance of RISC processors

Author

Obaidat, M.S. ; Abu-Saymeh, Dirar S.

Author_Institution

Dept. of Electr. & Comput. Eng., Missouri Univ., Columbia, MO, USA

fYear

1991

fDate

3-5 Apr 1991

Firstpage

213

Lastpage

222

Abstract

A methodology is devised to simulate and evaluate the performance of RISC processors. The detailed model provides a way to evaluate the performance of the processor for various applications and under a wide spectrum of operation environments and conditions. The instruction flow of each instruction is modeled. The instruction requests the various units and stages of pipelines which are modeled as resources. The model is applied on the Motorola MC88100 RISC processor which includes four processing units and numerous pipelines to speed up the execution of instructions. From the model the processing speed is investigated for various applications, and the contention on some units is studied. Moreover, the utilization of units and mean waiting time are studied and discussed

Keywords

instruction sets; performance evaluation; reduced instruction set computing; Motorola MC88100 RISC processor; RISC processors; instruction flow; mean waiting time; operation environments; performance; pipelines; processing speed; processing units; Application software; Benchmark testing; Central Processing Unit; Computational modeling; Computer aided instruction; Computer simulation; Laboratories; Microprocessors; Pipeline processing; Reduced instruction set computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Applied Computing, 1991., [Proceedings of the 1991] Symposium on

Conference_Location

Kansas City, MO

Print_ISBN

0-8186-2136-2

Type

conf

DOI

10.1109/SOAC.1991.143877

Filename

143877