New triple-transistor based defect-tolerant systems for reliable digital architectures

In this paper, we have proposed a new defect tolerant technique by adding redundancy at transistor level, where each transistor is replaced by three transistors placed in a special way such that reliability of the whole structure increases. The new triple-transistor redundancy technique offers a good reliability at lower area and delay overheads compared to most of the popular static fault tolerant techniques and can be used in designing various fault tolerant digital architectures to increase their reliabilities.