• DocumentCode
    33218
  • Title

    A 0.25 V 460 nW Asynchronous Neural Signal Processor With Inherent Leakage Suppression

  • Author

    Liu, T.-T. ; Rabaey, Jan M.

  • Author_Institution
    Berkeley Wireless Research Center, University of California, Berkeley,
  • Volume
    48
  • Issue
    4
  • fYear
    2013
  • fDate
    Apr-13
  • Firstpage
    897
  • Lastpage
    906
  • Abstract
    Further power and energy reductions via technology and voltage scaling have become extremely difficult due to leakage and variability issues. In this paper, we present a robust and energy-efficient computation architecture exploiting an asynchronous timing strategy to dynamically minimize leakage and to self-adapt to process variations and different operating conditions. Based on a logic topology with built-in leakage suppression, the prototype asynchronous neural signal processor demonstrates robust sub-threshold operation down to 0.25 V, while consuming only 460 nW in 0.03 {\\rm mm}^{2} in a 65 nm CMOS technology. These results represent a 4.4 \\times reduction in power, a 3.7 \\times reduction in energy and a 2.2 \\times reduction in power density, when compared to the state-of-the-art processors.
  • Keywords
    CMOS integrated circuits; Delay; Design methodology; Logic gates; Protocols; Robustness; Adaptive design; asynchronous circuits; energy-efficient circuits; neural signal processor; subthreshold CMOS circuits; ultra low voltage (ULV) design; variation-aware;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2013.2239096
  • Filename
    6423219